1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more specifically, it relates to a semiconductor device comprising a capacitor in a logic circuit area and a method of fabricating the same.
2. Description of the Background Art
In general, a semiconductor device such as a DRAM (dynamic random access memory) has a peripheral circuit area provided with a control logic circuit or the like around a memory cell area. A capacitor is generally employed in the logic circuit of the peripheral circuit area.
FIG. 41 is a sectional view showing a conventional semiconductor device (DRAM). The structure of the conventional semiconductor device is now described with reference to FIG. 41.
Referring to FIG. 41, the conventional semiconductor device comprises a memory cell area and a peripheral circuit area. The memory cell area is provided with field-effect transistors, a bit line 121, capacitors, and a metal wire 130. The peripheral circuit area is provided with a capacitor employed in a logic circuit.
In the memory cell area, field oxide films 102 are formed on a major surface of a semiconductor substrate 101. Source/drain regions 112, 113 and 114 are provided on the major surface of the semiconductor substrate 101 in an active region held between the field oxide films 102, to hold channel regions therebetween. Gate insulating films 132a and 132b are formed on the channel regions. Polysilicon films 106 are formed on the gate insulating films 132a and 132b. Tungsten silicide films 107 are formed on the polysilicon films 106. The polysilicon films 106 and the tungsten silicide films 107 form gate electrodes 110a and 110b. A first interlayer isolation film 115 is formed on the major surface of the semiconductor substrate 101 and the gate electrodes 110a and 110b. The first interlayer isolation film 115 is partially removed in a region positioned on the source/drain region 113, to define an opening 117. A polysilicon film 118 is formed in the opening 117 and on the first interlayer isolation film 115, to be in contact with the source/drain region 113. A tungsten silicide film 119 is formed on the polysilicon film 118. The polysilicon film 118 and the tungsten silicide film 119 form the bit line 121.
A second interlayer isolation film 122 is formed on the bit line 121 and the first interlayer isolation film 115. The first and second interlayer isolation films 115 and 122 are partially removed in regions positioned on the source/drain regions 112 and 114, to define openings 123 and 124. Lower electrodes 125 and 126 of capacitors consisting of polysilicon are formed in the openings 123 and 124 and on the second interlayer isolation film 122, to be in contact with the source/drain regions 112 and 114. Insulating films 142 for serving as dielectric films of the capacitors are formed on the lower electrodes 125 and 126. Upper electrodes 127 of the capacitors are formed on the insulating films 142. A third interlayer isolation film 128 is formed on the upper electrodes 127 and the second interlayer isolation film 122. The metal wire 130 is formed on the third interlayer isolation film 128.
The peripheral circuit area is provided with a capacitor. FIG. 41 shows sections of the capacitor taken along the lines 500--500 and 600--600 in FIG. 42 respectively. The positional relation between the lines 500--500 and 600--600 is described with reference to FIG. 42. FIG. 42 is a plan view typically showing the structure of the capacitor provided in the peripheral circuit area. Referring to FIG. 42, the line 500--500 is located on a portion of electrodes of the capacitor, and the line 600--600 is located on a portion provided with openings 138 and 139.
Referring again to FIG. 41, field oxide films 102 are formed on the major surface of the semiconductor substrate 101 in the section of the peripheral circuit area taken along the line 500--500. An insulating film 131 is formed on the major surface of the semiconductor substrate 101 in an active region held between the field oxide films 102. A polysilicon film 106 is formed on the insulating film 131. A tungsten silicide film 107 is formed on the polysilicon film 106. The polysilicon film 106 and the tungsten silicide film 107 form a lower electrode 111 of the capacitor provided in the peripheral circuit area. The first interlayer isolation film 115 is formed on the lower electrode 111 of the capacitor. A polysilicon film 118 is formed on the first interlayer isolation film 115. A tungsten silicide film 119 is formed on the polysilicon film 118. The polysilicon film 118 and the tungsten silicide film 119 form an upper electrode 120 of the capacitor in the peripheral circuit area. The second interlayer isolation film 122 is formed on the upper electrode 120 and the first interlayer isolation film 115. The third interlayer isolation film 128 is formed on the second interlayer isolation film 122.
In the section of the peripheral circuit area taken along the line 600--600, field oxide films 102 are formed on the major surface of the semiconductor substrate 101. An insulating film 131 is formed on a prescribed region of the major surface of the semiconductor substrate 101 in an active region held between the field oxide films 102. A polysilicon film 106 is formed on the insulating film 131. A tungsten silicide film 107 is formed on the polysilicon film 106. The polysilicon film 106 and the tungsten silicide film 107 form a connecting region 143 partially forming the lower electrode 111 of the capacitor provided in the peripheral circuit area. The first interlayer isolation film 115 is formed on the connecting region 143 and the major surface of the semiconductor substrate 101. A polysilicon film 118 is formed on a region of the first interlayer isolation film 115 positioned on the connecting region 143. A tungsten silicide film 119 is formed on the polysilicon film 118. The polysilicon film 118 and the tungsten silicide film 119 form a connecting region 144 partially forming the upper electrode 120 of the capacitor in the peripheral circuit area. The second interlayer isolation film 122 is formed on the connecting region 144 and the first interlayer isolation film 115. The third interlayer isolation film 128 is formed on the second interlayer isolation film 122.
The first to third interlayer isolation films 115, 122 and 128 are partially removed in regions positioned on the connecting region 143, to define the opening 139. Further, the second and third interlayer isolation films 122 and 128 are partially removed in regions positioned on the connecting region 144, to define the opening 138. A metal wire 135 is formed in the opening 139 and on the third interlayer isolation film 128, to be in contact with the connecting region 143. Another metal wire 134 is formed in the opening 138 and on the third interlayer isolation film 128, to be in contact with the connecting region 144. Thus, the lower electrode 111, the upper electrode 120 and a part of the first interlayer isolation film 155 located between the upper and lower electrodes 120 and 111 for serving as a dielectric film form the capacitor in the peripheral circuit area. FIG. 43 is an equivalent circuit diagram of the capacitor in the peripheral circuit area.
FIGS. 44 to 59 are sectional views for illustrating steps of fabricating the conventional semiconductor device (DRAM). The steps of fabricating the conventional semiconductor device are now described with reference to FIGS. 44 to 59.
First, an oxide film 103 (see FIG. 44) is formed on the major surface of the semiconductor substrate 101 (see FIG. 44). A nitride film 104 (see FIG. 44) is formed on the oxide film 103. Resist patterns (not shown) are formed on the nitride film 104, and employed as masks for partially removing the oxide film 103 and the nitride film 104. Then, the major surface of the semiconductor substrate 101 is oxidized, to form the field oxide films 102 (see FIG. 44). Thus, the structure shown in FIG. 44 is obtained. Then, the remaining nitride and oxide films 104 and 103 are removed from the major surface of the semiconductor substrate 101, to obtain the structure shown in FIG. 45.
Then, an oxide film 105 is formed on the major surface of the semiconductor substrate 101, as shown in FIG. 46. A polysilicon film 106 is formed on the oxide film 105 and the field oxide films 102. A tungsten silicide film 107 is formed on the polysilicon film 106. Resist patterns 108 and 109 are formed on the tungsten silicide film 107.
Then, the tungsten silicide film 107, the polysilicon film 106 and the oxide film 105 are partially removed by etching through the resist patterns 108 and 109 serving as masks. Thereafter the resist patterns 108 and 109 are removed. Thus, the structure shown in FIG. 47 is obtained. The polysilicon films 106 and the tungsten silicide films 107 form the gate electrodes 110a and 110b of the field-effect transistors in the memory cell area. In the peripheral circuit area, the polysilicon film 106 and the tungsten silicide film 107 form the lower electrode 111 and the connecting region 143 of the capacitor.
Then, impurity ions are implanted into prescribed regions of the major surface of the semiconductor substrate 101 in the memory cell area, to form the source/drain regions 112, 113 and 114 (see FIG. 48). Thus, the structure shown in FIG. 48 is obtained.
Then, the first interlayer isolation film 115 is formed on the gate electrodes 110a and 110b and the lower electrode 111 and the connecting region 143 of the capacitor in the peripheral circuit area, as shown in FIG. 49. Resist patterns 116 are formed on the first interlayer isolation film 115.
Then, the first interlayer isolation film 115 is partially removed by anisotropic etching through the resist patterns 116 serving as masks, to define the opening 117 (see FIG. 50). Thereafter the resist patterns 116 are removed. Thus, the structure shown in FIG. 50 is obtained.
Then, a polysilicon film 118 is formed in the opening 117 and on the first interlayer isolation film 115, as shown in FIG. 51. A tungsten silicide film 119 is formed on the polysilicon film 118.
Then, resist patterns (not shown) are formed on the tungsten silicide film 119, and employed as masks for partially removing the tungsten silicide film 119 and the polysilicon film 118 by etching. Thus, the bit line 121 in the memory cell area and the upper electrode 120 and the connecting region 144 of the capacitor in the peripheral circuit area are formed as shown in FIG. 52. The bit line 121 and the upper electrode 120 and the connecting region 144 of the capacitor in the peripheral circuit area are formed by the polysilicon films 118 and the tungsten silicide films 119 respectively.
Then, the second interlayer isolation film 122 (see FIG. 53) is formed on the bit line 121, the upper electrode 120 and the connecting region 144 of the capacitor in the peripheral circuit area and the first interlayer isolation film 115. Resist patterns (not shown) are formed on the second interlayer isolation film 122 and employed as masks for partially removing the first and second interlayer isolation films 115 and 122 by etching, to define the openings 123 and 124 (see FIG. 53). Thereafter the resist patterns are removed. Thus, the structure shown in FIG. 53 is obtained.
Then, a polysilicon film (not shown) is formed in the openings 123 and 124 and on the second interlayer isolation film 122. Resist patterns (not shown) are formed on the polysilicon film and employed as masks for partially removing the polysilicon film by anisotropic etching, to form the lower electrodes 125 and 126 (see FIG. 54) of the capacitors in the memory cell area. Thereafter the resist patterns are removed. Thus, the structure shown in FIG. 54 is obtained.
Then, an oxide film (not shown) is formed on the lower electrodes 125 and 126 and the second interlayer isolation film 122. A polysilicon film (not shown) is formed on the oxide film. Resist patterns (not shown) are formed on the polysilicon film and employed as masks for partially removing the polysilicon film and the oxide film. Thereafter the resist patterns are removed. Thus, the upper electrodes 127 of the capacitors in the memory area and the oxide films 142 for serving as dielectric films are formed as shown in FIG. 55.
Then, the third interlayer isolation film 128 is formed on the upper electrodes 127 of the capacitors and the second interlayer isolation film 122, as shown in FIG. 56.
Then, resist patterns 136 are formed on the third interlayer isolation film 128, as shown in FIG. 57.
Then, the first to third interlayer isolation films 115, 122 and 128 are partially removed by anisotropic etching through the resist patterns 136 serving as masks, to define the openings 138 and 139 (see FIG. 58) in the peripheral circuit area. Thereafter the resist patterns 136 are removed, to obtain the structure shown in FIG. 58. At this time, surfaces of the connecting regions 143 and 144 are partially exposed on bottom portions of the openings 138 and 139 respectively.
Then, a metal layer 129 is formed in the openings 138 and 139 and on the third interlayer isolation film 128, as shown in FIG. 59.
Then, resist patterns (not shown) are formed on the metal layer 129 and employed as masks for partially removing the metal layer 129 by anisotropic etching, and the resist patterns are removed, to obtain the structure shown in FIG. 41.
The conventional semiconductor device is fabricated in the aforementioned manner.
In recent years, refinement and high integration of a semiconductor device are increasingly required. In order to increase the degree of integration of a DRAM, for example, it is important to refine not only elements in a memory cell area but those in a peripheral circuit area. In the peripheral circuit area of the DRAM, capacitors occupy 20 to 30% of its area. Further, a capacitance exceeding a certain constant value must be ensured for the capacitor in the peripheral circuit area, since a driving voltage is not remarkably reduced following size reduction of the semiconductor device. Following refinement and high integration of the semiconductor device, therefore, it is necessary to reduce the occupied area of the capacitor while ensuring a capacitance exceeding a constant value for the capacitor.
In the capacitor formed in the peripheral circuit area of the conventional semiconductor device, the depths of the openings 138 and 139 simultaneously formed by etching are different from each other, as shown in FIG. 58. After the opening 138 reaches the surface of the connecting region 144, therefore, the surface of the connecting region 144 is still continuously etched on the bottom portion of the opening 138 until the opening 139 reaches the connecting region 143. Thus, the opening 138 may pass through the connecting region 144 to reach the connecting region 143, as shown in FIG. 60. In this case, the capacitor formed in the peripheral circuit area disadvantageously loses its function, due to short-circuiting across the upper and lower electrodes 120 and 111 (see FIG. 41). This results in a significant problem with size reduction of the capacitor in the peripheral circuit area following refinement and high integration of the semiconductor device. In refinement and high integration of the semiconductor device, therefore, required is a highly reliable capacitor which will not lose its function.
On the other hand, the steps of fabricating the capacitor in the peripheral circuit area must be based on utilization of conductive layers etc. in the steps of fabricating the elements in the memory cell area for minimizing the number of the steps, in order to reduce the fabrication cost. Therefore, a technique of stereoscopically complicating the shapes of electrodes of capacitors for increasing the surface areas thereof, which is applied to the capacitances of the capacitors in the memory cell area, is not applied to the capacitor in the peripheral circuit area, since this results in complication of the fabrication steps and increase of the number thereof. Thus, awaited is a highly reliable capacitor structure and a method of fabricating the same which can reduce the occupied area of the capacitor while ensuring a constant capacitance with no complication of fabrication steps.